Improved Algorithms for Point Placement

Signal Integrity plays a crucial role in high performance systems. Designers spend signiicant amounts of time in deciding correct circuit topologies which yield acceptable noise and delay margins. Our work on signal integrity driven placement focuses on algorithms which obey signal integrity toplogy constraints. Given a set of chips, the associated pin-to-pin delay requirements and a layout board, the principal concern is to achieve a placement of the chips on the board such that the delay constraints are satissed. In this paper we abstract this problem as that of of embedding a graph on a grid. The edges of the graph denote bounding distances between the vertices. The board is a rectangular matrix containing keep-outs, rooms and free estate. We present an algorithm based on Graph Sparsiication that is theoretically sound and easy to implement. The fundamental contribution of this paper is the concept of Binary Grid Splitting which exploits certain structures in the input to produce algorithms that are useful in practice. Our results quantify the running time of the algorithm in terms of an inherent property of the input graph called its placement radius.